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lh28f800su 1 8m (512k 16, 1m 8) flash memory figure 1. tsop reverse bend configuration features ? user-configurable x8 or x16 operation ? user-selectable 3.3 v or 5 v v cc ? 5 v write/erase operations (5 v v pp ) C no requirement for dc/dc converter to write/erase ? 70 ns maximum access time ? minimum 2.7 v read capability C 160 ns maximum access time (v cc = 2.7 v) ? 16 independently lockable blocks ? 0.32 mb/sec write transfer rate ? 100,000 erase cycles per block ? revolutionary architecture C pipelined command execution C write during erase C command superset of sharp lh28f008sa ? 5 a (typ.) i cc in cmos standby ? 1 a (typ.) deep power-down ? state-of-the-art 0.55 m etox? flash technology ? 56-pin, 1.2 mm 14 mm 20 mm tsop (type i) package 28f800sur-1 top view 56-pin tsop 2 3 4 5 8 9 a 16 a 19 53 52 51 50 49 48 45 42 nc nc 6 7 a 17 a 18 47 46 ry/by dq 15 dq 14 gnd gnd 10 11 12 55 54 oe v cc 13 44 dq 4 43 v cc a 15 dq 7 14 15 16 17 18 19 20 39 36 41 40 38 37 dq 3 dq 10 dq 2 v cc a 10 a 9 a 11 v pp rp ce 0 a 8 dq 9 we dq 6 dq 13 dq 11 56 1 ce 1 3/5 wp 21 22 23 24 25 26 27 28 a 4 a 3 a 5 a 7 a 6 gnd a 2 a 1 34 dq 8 35 dq 1 31 33 32 30 29 a 0 byte nc nc dq 0 a 14 a 13 a 12 dq 5 dq 12
lh28f800su 8m (512k 16, 1m 8) flash memory 2 introduction sharps lh28f800su 8m flash memory is a revolu- tionary architecture which enables the design of truly mobile, high performance, personal computing and com- munication products. with innovative capabilities, 5 v single voltage operation and very high read/write per- formance, the lh28f800su is also the ideal choice for designing embedded mass storage flash memory sys- tems. the lh28f800su is a very high density, highest per- formance non-volatile read/write solution for solid-state storage applications. its symmetrically blocked archi- tecture (100% compatible with the lh28f008sa 8m flash memory, the lh28f016sa 16m flash memory and the lh28f016su 16m 5 v single voltage flash memory), extended cycling, low power 3.3 v operation, very fast write and read performance and selective block locking provide a highly flexible memory component suit- able for high density memory cards, resident flash arrays and pcmcia-ata flash drives. the lh28f800sus dual read voltage enables the design of memory cards which can interchangeably be read/writ- ten in 3.3 v and 5.0 v systems. its x8/x16 architecture allows the optimization of memory to processor inter- face. the flexible block locking option enables bundling of executable application software in a resident flash array or memory card. manufactured on sharps 0.55 m etox? process technology, the lh28f800su is the most cost-effective, high-density 3.3 v flash memory. description the lh28f800su is a high performance 8m (8,388,608 bit) block erasable non-volatile random access memory organized as either 512k 16 or 1m 8. the lh28f800su includes sixteen 64k (65,536) blocks or sixteen 32-kw (32,768) blocks. a chip memory map is shown in figure 3. the implementation of a new architecture, with many enhanced features, will improve the device operating characteristics and results in greater product reliability and ease of use. among the significant enhancements of the lh28f800su: ? 5 v write/erase operation (5 v v pp ) ? 3.3 v low power capability (2.7 v v cc read) ? improved write performance ? dedicated block write/erase protection a 3/5 ? input pin reconfigures the device internally for optimized 3.3 v or 5.0 v read/write operation. figure 2. tsop configuration 28f800sur-17 top view 56-pin tsop 2 3 4 5 8 9 a 16 a 19 53 52 51 50 49 48 45 42 nc nc 6 7 a 17 a 18 47 46 ry/by dq 15 dq 14 gnd gnd 10 11 12 55 54 oe v cc 13 44 dq 4 43 v cc a 15 dq 7 14 15 16 17 18 19 20 39 36 41 40 38 37 dq 3 dq 10 dq 2 v cc a 10 a 9 a 11 v pp rp ce 0 a 8 dq 9 we dq 6 dq 13 dq 11 56 1 ce 1 3/5 wp 21 22 23 24 25 26 27 28 a 4 a 3 a 5 a 7 a 6 gnd a 2 a 1 34 dq 8 35 dq 1 31 33 32 30 29 a 0 byte nc nc dq 0 a 14 a 13 a 12 dq 5 dq 12
8m (512k 16, 1m 8) flash memory lh28f800su 3 figure 3. lh28f800su block diagram (architectural evolution includes page buffers, queue registers and extended status registers) output buffer output buffer input buffer input buffer dq 0 - dq 7 dq 8 - dq 15 id register output multiplexer csr esrs data comparator data queue registers page buffers cui wsm 64kb block 0 64kb block 1 64kb block 14 64kb block 15 . . . . . . y gating/sensing y-decoder x-decoder program/ erase voltage switch v pp 3/5 v cc gnd ry/by address counter address queue latches input buffer a 0 - a 19 . . . 28f800sur-2 i/o logic rp wp we oe ce 0 ce 1 3/5 byte
lh28f800su 8m (512k 16, 1m 8) flash memory 4 pin description symbol type name and function a 0 input byte-select address: selects between high and low byte when device is in x8 mode. this address is latched in x8 data writes. not used in x16 mode (i.e., the a 0 input buffer is turned off when byte is high). a 1 - a 15 input word-select addresses: select a word within one 64k block. a 6 - a 15 selects 1 of 1024 rows, and a 1 - a 5 selects 16 of 512 columns. these addresses are latched during data writes. a 16 - a 19 input block-select addresses: select 1 of 16 erase blocks. these addresses are latched during data writes, erase and lock-block operations. dq 0 - dq 7 input/output low-byte data bus: inputs data and commands during cui write cycles. outputs array, buffer, identifier or status data in the appropriate read mode. floated when the chip is de-selected or the outputs are disabled. dq 8 - dq 15 input/output high-byte data bus : inputs data during x16 data-write operations. outputs array, buffer or identifier data in the appropriate read mode; not used for status register reads. floated when the chip is de-selected or the outputs are disabled. ce ? 0 , ce ? 1 input chip enable inputs : activate the devices control logic, input buffers, decoders and sense amplifiers. with either ce ? 0 or ce ? 1 high, the device is de-selected and power consumption reduces to standby levels upon completion of any current data-write or erase operations. both ce ? 0 , ce ? 1 must be low to select the device. all timing specifications are the same for both signals. device selection occurs with the latter falling edge of ce ? 0 or ce ? 1 . the first rising edge of ce ? 0 or ce ? 1 disables the device. rp ? input reset/power-down: with rp ? low, the device is reset, any current operation is aborted and device is put into the deep power down mode. when the power is turned on, rp ? pin is turned to low in order to return the device to default configuration. when the 3/5 ? pin is switched, or when the power transition is occurred, or at the power on/off, rp ? is required to stay low in order to protect data from noise. when returning from deep power-down, a recovery time of 400 ns (v cc +5.0 v 0.25 v) is required to allow these circuits to power-up. when rp ? goes low, any current or pending wsm operation(s) are terminated, and the device is reset. all status registers return to ready (with all status flags cleared). after returning, the device is in read array mode. oe ? input output enable: gates device data through the output buffers when low. the outputs float to tri-state off when oe ? is high. note: ce ? x overrides oe ? , and oe ? overrides we. we input write enable: controls access to the cui, page buffers, data queue registers and address queue latches. we is active low, and latches both address and data (command or array) on its rising edge. ry ? /by ? open drain output ready/busy: indicates status of the internal wsm. when low, it indicates that the wsm is busy performing an operation. ry ? /by ? high indicates that the wsm is ready for new operations (or wsm has completed all pending operations), or erase is suspended, or the device is in deep power-down mode. this output is always active (i.e., not floated to tri-state off when oe ? or ce ? 0 , ce ? 1 are high), except if a ry ? /by ? pin disable command is issued.
8m (512k 16, 1m 8) flash memory lh28f800su 5 pin description (continued) symbol type name and function wp input write protect: erase blocks can be locked by writing a non-volatile lock-bit for each block. when wp is low, those locked blocks as reflected by the block-lock status bits (bsr.6), are protected from inadvertent data writes or erases. when wp is high, all blocks can be written or erased regardless of the state of the lock-bits. the wp input buffer is disabled when rp ? transitions low (deep power-down mode). byte input byte enable: byte low places device x8 mode. all data is then input or output on dq 0 - dq 7 , and dq 8 - dq 15 float. address a 0 selects between the high and low byte. byte high places the device in x16 mode, and turns off the a 0 input buffer. address a 1 , then becomes the lowest order address. 3/5 ? input 3.3/5.0 volt select: 3/5 ? high configures internal circuits for 3.3 v operation. 3/5 ? low configures internal circuits for 5.0 v operation. notes: reading the array with 3/5 ? high in a 5.0 v system could damage the device. there is a significant delay from 3/5 ? switching to valid data. v pp supply erase/write power supply (5.0 v 0.5 v) : for erasing memory array blocks or writing words/bytes/pages into the flash array. v cc supply device power supply (3.3 v 0.3 v, 5.0 v 0.5 v) (2.7 ~ 3.6 at read operation) : do not leave any power pins floating. gnd supply ground for all internal circuitry: do not leave any ground pins floating. nc no connect: no internal connection to die, lead may be driven or left floating.
lh28f800su 8m (512k 16, 1m 8) flash memory 6 the lh28f800su will be available in a 56-pin, 1.2 mm thick 14 mm 20 mm tsop (type i) pack- age. this form factor and pinout allow for very high board layout densities. a command user interface (cui) serves as the sys- tem interface between the microprocessor or microcontroller and the internal memory operation. internal algorithm automation allows byte/word writes and block erase operations to be executed using a tw o-write command sequence to the cui in the same way as the lh28f008sa 8m flash memory. a superset of commands have been added to the basic lh28f008sa command-set to achieve higher write performance and provide additional capabilities. these new commands and features include: ? page buffer writes to flash ? command queuing capability ? automatic data writes during erase ? software locking of memory blocks ? two-byte successive writes in 8-bit systems ? erase all unlocked blocks writing of memory data is performed in either byte or word increments typically within 8 s, a 25% improve- ment over the lh28f008sa. a block erase operation erases one of the 16 blocks in typically 0.7 seconds, independent of the other blocks, which is about 55% improvement over the lh28f008sa. the lh28f800su incorporates two page buffers of 256 bytes (128 words) each to allow page data writes. this feature can improve a system write performance over previous flash memory devices. all operations are started by a sequence of write commands to the device. three status registers (de- scribed in detail later) and a ry ? /by ? output pin provide information on the progress of the requested operation. while the lh28f008sa requires an operation to com- plete before the next operation can be requested, the lh28f800su allows queuing of the next operation while the memory executes the current operation. this elimi- nates system overhead when writing several bytes in a row to the array or erasing several blocks at the same time. the lh28f800su can also perform write opera- tions to one block of memory while performing erase of another block. the lh28f800su provides user-selectable block locking to protect code or data such as device drivers, pcmcia card information, rom-executable o/s or ap- plication code. each block has an associated non- volatile lock-bit which determines the lock status of the block. in addition, the lh28f800su has a master write protect pin (wp ? ) which prevents any modification to memory blocks whose lock-bits are set. the lh28f800su contains three types of status registers to accomplish various functions: ? a compatible status register (csr) which is 100% compatible with the lh28f008sa flash memorys status register. this register, when used alone, provides a straightforward upgrade capabil- ity to the lh28f800su from a lh28f008sa based design. ? a global status register (gsr) which informs the system of command queue status. page buffer sta- tus, and overall write state machine (wsm) status. ? 16 block status register (bsrs) which provide block-specific status information such as the block lock-bit status. the gsr and bsr memory maps for byte-wide and word-wide modes are shown in figures 5 and 6. the lh28f800su incorporates an open drain ry ? /by ? output pin. this feature allows the user to or- tie many ry ? /by ? pins together in a multiple memory con- figuration such as a resident flash array. the lh28f800su also incorporates a dual chip-en- able function with two input pins. ce ? 0 and ce ? 1 . these pins have exactly the same functionality as the regular chip-enable pin ce ? on the lh28f008sa. for minimum chip designs, ce ? 1 may be tied to ground and use ce ? 0 as the chip enable input. the lh28f800su uses the logical combination of these two signals to enable or disable the entire chip. both ce ? 0 and ce ? 1 must be ac- tive low to enable the device and if either one becomes inactive, the chip will be disabled. this fea- ture, along with the open drain ry ? /by ? pin, allows the system designer to reduce the number of control pins used in a large array of 8m devices. the by ? te ? pin allows either x8 or x16 read/writes to the lh28f800su. by ? te ? at logic low selects 8-bit mode with address a 0 selecting between low byte and high byte. on the other hand, by ? te ? at logic high enables 16-bit operation with address a 1 becoming the lowest order address and address a 0 is not used (dont care). a block diagram is shown in figure 3. the lh28f800su is specified for a maximum access time of each version, as follows: operating temperature v cc supply max. access (t acc ) 0 - 70c 4.75 - 5.25 v 70 ns 0 - 70c 4.5 - 5.5 v 80 ns 0 - 70c 3.0 - 3.6 v 120 ns 0 - 70c 2.7 - 3.6 v 160 ns
8m (512k 16, 1m 8) flash memory lh28f800su 7 figure 4. lh28f800su memory map (byte-wide mode) the lh28f800su incorporates an automatic power saving (aps) feature which substantially reduces the active current when the device is in static mode of operation (addresses not switching). in aps mode, the typical i cc current is 2 ma at 5.0 v (1 ma at 3.3 v). a deep power-down mode of operation is invoked when the rp ? (called pwd on the lh28f008sa) pin transitions low, any current operation is aborted and the device is put into the deep power-down mode. this mode brings the device power consumption to less than 5 a, typically, and provides additional write protection by acting as a device reset pin during power transitions. when the power is turned on, rp ? pin turned to low or- der to return the device to default configuration. when the 3/5 ? pin is switched, or when the power transition is occurred, or at the power on/off, rp ? is required to stay low in order to protect data from noise. a recovery time of 400 ns (v cc = 5.0 v 0.5 v) is required from rp ? switching high until outputs are again valid. in the deep power-down state, the wsm is reset (any current operation will abort) and the csr, gsr and bsr regis- ters are cleared. a cmos standby mode of operation is enabled when either ce ? 0 or ce ? 1 transitions high and rp ? stays high with all input control pins at cmos levels. in this mode, the device typically draws an i cc standby cur- rent of 10 a. fffffh 15 f0000h effffh 14 e0000h dffffh 13 d0000h cffffh 12 c0000h bffffh 11 b0000h affffh 10 a0000h 9ffffh 9 90000h 8ffffh 8 80000h 7ffffh 7 70000h 6ffffh 6 60000h 5ffffh 5 50000h 4ffffh 4 40000h 3ffffh 3 30000h 2ffffh 2 20000h 1ffffh 1 10000h 0ffffh 0 00000h 64kb block 64kb block 64kb block 64kb block 64kb block 64kb block 64kb block 64kb block 64kb block 64kb block 64kb block 64kb block 64kb block 64kb block 64kb block 64kb block 28f800sur-3 memory map
lh28f800su 8m (512k 16, 1m 8) flash memory 8 figure 5. extended status register memory map (byte-wide mode) figure 6. extended status register memory map (word-wide mode) reserved gsr reserved bsr15 reserved reserved f0006h f0005h f0004h f0003h f0002h f0001h f0000h a[19:0] x8 mode . . . reserved gsr reserved bsr0 reserved reserved 00006h 00005h 00004h 00003h 00002h 00001h 00000h reserved 10002h 28f800sur-4 reserved gsr reserved bsr15 reserved reserved 78003h 78002h 78001h 78000h a[19:1] (note) x16 mode . . . reserved gsr reserved bsr0 reserved reserved 00003h 00002h 00001h 00000h reserved 08001h 28f800sur-5 note: in word-wide mode a 0 don't care, address values are ignored a 0 .
8m (512k 16, 1m 8) flash memory lh28f800su 9 bus operations, commands and status register definitions bus operations for word-wide mode (by ? te ? = v ih ) mode rp ? ce ? 1 ce ? 0 oe ? we a 1 dq 0 - dq 15 ry ? /by ? note read v ih v il v il v il v ih xd out x1, 2, 7 output disable v ih v il v il v ih v ih x high-z x 1, 6, 7 standby v ih v il v ih v ih v ih v il v ih x x x high-z x 1, 6, 7 deep power-down v il xxxxx high-z v oh 1, 3 manufacturer id v ih v il v il v il v ih v il 00b0h v oh 4 device id v ih v il v il v il v ih v ih 66a8h v oh 4 write v ih v il v il v ih v il xd in x1, 5, 6 notes: 1. x can be v ih or v il for address or control pins except for ry ? /by ? , which is either v ol or v oh . 2. ry ? /by ? output is open drain. when the wsm is ready, erase is suspended or the device is in deep power-down mode, ry ? /by ? will be at v oh if it is tied to v cc through a resistor. when the ry ? /by ? at v oh is independent of oe ? while a wsm operation is in progress. 3. rp ? at gnd 0.2 v ensures the lowest deep power-down current. 4. a 0 and a 1 at v il provide manufacturer id codes in x8 and x16 modes respectively. a 0 and a 1 , at v ih provide device id codes in x8 and x16 modes respectively. all other addresses are set to zero. 5. commands for different erase operations, data write operations of lock-block operations can only be successfully completed when v pp = v pph . 6. while the wsm is running, ry ? /by ? in level-mode (default) stays at v ol until all operations are complete. ry ? /by ? goes to v oh when the wsm is not busy or in erase suspend mode. 7. ry ? /by ? may be at v ol while the wsm is busy performing various operations. for example, a status register read during a write operations. bus operations for byte-wide mode (by ? te ? = v il ) mode rp ? ce ? 1 ce ? 0 oe ? we a 0 dq 0 - dq 7 ry ? /by ? note read v ih v il v il v il v ih xd out x1, 2, 7 output disable v ih v il v il v ih v ih x high-z x 1, 6, 7 standby v ih v il v ih v ih v ih v il v ih x x x high-z x 1, 6, 7 deep power-down v il xxxxx high-z v oh 1, 3 manufacturer id v ih v il v il v il v ih v il b0h v oh 4 device id v ih v il v il v il v ih v ih a8h v oh 4 write v ih v il v il v ih v il xd in x1, 5, 6
lh28f800su 8m (512k 16, 1m 8) flash memory 10 command first bus cycle second bus cycle note oper. address data oper. address data read array write x ffh read aa ad intelligent identifier write x 90h read ia id 1 read compatible status register write x 70h read x csrd 2 clear status register write x 50h 3 word/byte write write x 40h write wa wd alternate word/byte write write x 10h write wa wd block erase/confirm write x 20h write ba d0h erase suspend/resume write x b0h write x d0h address data aa = array address ad = array data ba = block address csrd = csr data ia = identifier address id = identifier data wa = write address wd = write data x = dont care notes: 1. following the intelligent identifier command, two read operations access the manufacturer and device signature codes. 2. the csr is automatically available after device enters data write, erase or suspend operations. 3. clears csr.3, csr.4, and csr.5. also clears gsr.5 and all bsr.5 and bsr.2 bits. see status register definitions. lh28f008sa-compatible mode command bus definitions
8m (512k 16, 1m 8) flash memory lh28f800su 11 lh28f800su performance enhancement command bus definitions command mode first bus cycle second bus cycle third bus cycle note oper. addr. data oper. addr. data oper. addr. data read extended status register write x 71h read ra gsrd bsrd 1 page buffer swap write x 72h 7 read page buffer write x 75h read pa pd single load to page buffer write x 74h write pa pd sequential load to page buffer x8 write x e0h write x bcl write x bch 4, 6, 10 x16 write x e0h write x wcl write x wch 4, 5, 6, 10 page buffer write to flash x8 write x 0ch write a0 bc (l, h) write wa bc (h, l) 3, 4, 9, 10 x16 write x 0ch write x wcl write wa wch 4, 5, 10 two-byte write x8 write x fbh write a0 wd (l, h) write wa wd (h, l) 3 block erase/confirm write x 20h write ba d0h lock block/confirm write x 77h write ba d0h upload status bits/confirm write x 97h write x d0h 2 upload device information write x 99h write x d0h erase all unlocked blocks/confirm write x a7h write x d0h ry ? /by ? enable to level-mode write x 96h write x 01h 8 ry ? /by ? pulse-on- write write x 96h write x 02h 8 ry ? /by ? pulse-on- erase write x 96h write x 03h 8 ry ? /by ? disable write x 96h write x 04h 8 sleep write x f0h abort write x 80h address data ba = block address ad = array data pa = page buffer address pd = page buffer data ra = extended register address bsrd = bsr data wa = write address gsrd = gsr data x = dont care wc (l, h) = word count (low, high) bc (l, h) = byte count (low, high) wd (l, h) = write data (low, high)
lh28f800su 8m (512k 16, 1m 8) flash memory 12 notes: 1. ra can be the gsr address or any bsr address. see figure 5 and 6 for extended status register memory maps. 2. upon device power-up, all bsr lock-bits come up locked. the upload status bits command must be written to reflect the actual lock- bit status. 3. a 0 is automatically complemented to load second byte of data. by ? te ? must be at v il . a 0 value determines which wd/bc is supplied first: a 0 = 0 looks at the wdl/bcl, a 0 = 1 looks at the wdh/bch. 4. bch/wch must be at 00h for this product because of the 256-byte (128 word) page buffer size and to avoid writing the page buffer contents into more than one 256-byte segment within an array block. they are simply shown for future page buffer expandability. 5. in x16 mode, only the lower byte dq 0 - dq 7 is used for wcl and wch. the upper byte dq 8 - dq 15 is a dont care. 6. pa and pd (whose count is given in cycles 2 and 3) are supplied starting in the 4th cycle which is not shown. 7. this command allows the user to swap between available page buffers (0 or 1). 8. these commands reconfigure ry ? /by ? output to one of two pulse-modes or enable and disable the ry ? /by ? function. 9. write address, wa, is the destination address in the flash array which must match the source address in the page buffer. refer to the lh28f800su users manual. 10. bcl = 00h corresponds to a byte count of 1. similarly, wcl = 00h corresponds to a word count of 1. wsms ess es dws vpps r r r 76543210 csr.7 = write state machine status (wsms) 1 = ready 0 = busy csr.6 = erase-suspend status (ess) 1 = erase suspended 0 = erase in progress/completed csr.5 = erase status (es) 1 = error in block erasure 0 = successful block erase csr.4 = data-write status (dws) 1 = error in data write 0 = data write successful csr.3 = v pp status (vpps) 1 = v pp low detect, operation abort 0 = v pp ok notes: 1. ry ? /by ? output or wsms bit must be checked to determine completion of an operation (erase suspend, erase or data write) before the appropriate status bit (ess, es or dws) is checked for success. 2. if dws and es are set to 1 during an erase attempt, an improper command sequence was entered. clear the csr and attempt the operation again. 3. the vpps bit, unlike an a/d converter, does not provide continuous indication of v pp level. the wsm interrogates v pp s level only after the data-write or erase command sequences have been entered, and informs the system if v pp has not been switched on. vpps is not guaranteed to report accurate feedback between v ppl and v pph . 4. csr.2 - csr.0 = reserved for future enhancements. these bits are reserved for future use and should be masked out when polling the csr. compatible status register
8m (512k 16, 1m 8) flash memory lh28f800su 13 wsms oss dos dss qs pbas pbs pbss 76543210 gsr.7 = write state machine status (wsms) 1 = ready 0 = busy gsr.6 = operation suspend status (oss) 1 = operation suspended 0 = operation in progress/completed gsr.5 = device operation status (dos) 1 = operation unsuccessful 0 = operation successful or currently running gsr.4 = device sleep status(dss) 1 = device in sleep 0 = device not in sleep matrix 5/4 00 = operation successful or currently running 01 = device in sleep mode or pending sleep 10 = operation unsuccessful 11 = operation unsuccessful or aborted gsr.3 = queue status (qs) 1 = queue full 0 = queue available gsr.2 = page buffer available status (pbas) 1 = one or two page buffers available 0 = no page buffer available gsr.1 = page buffer status (pbs) 1 = selected page buffer ready 0 = selected page buffer busy gsr.0 = page buffer select status (pbss) 1 = page buffer 1 selected 0 = page buffer 0 selected notes: 1. ry ? /by ? output or wsms bit must be checked to determine completion of an operation (block lock, suspend, any ry ? /by ? reconfiguration, upload status bits, erase or data write) before the appropriate status bit (oss or dos) is checked for success. 2. if operation currently running, then gsr.7 = 0. 3. if device pending sleep, then gsr.7 = 0. 4. operation aborted: unsucccessful due to abort command. 5. the device contains two page buffers. 6. selected page buffer is currently busy with wsm operation. 7. when multiple operations are queued, checking bsr.7 only provides indication of completion for that particular block. gsr.7 provides indication when all queued opera- tions are completed. global status register
lh28f800su 8m (512k 16, 1m 8) flash memory 14 bs bls bos boas qs vpps r r 76543210 bsr.7 = block status (bs) 1 = ready 0 = busy bsr.6 = block-lock status (bls) 1 = block unlocked for write/erase 0 = block locked for write/erase bsr.5 = block operation status (bos) 1 = operation unsuccessful 0 = operation successful or currently running bsr.4 = block operation abort status (boas) 1 = operation aborted 0 = operation not aborted matrix 5/4 00 = operation successful or currently running 01 = not a valid combination 10 = operation unsuccessful 11 = operation aborted bsr.3 = queue status (qs) 1 = queue full 0 = queue available bsr.2 = v pp status (v pps ) 1 = v pp low detect, operation abort 0 = v pp ok notes: 1. ry ? /by ? output or bs bit must be checked to determine completion of an operation (block lock, suspend, erase or data write) before the appropriate status bits (bos, bls) is checked for success. 2. the boas bit will not be set until bsr.7 = 1. 3. operation halted via abort command. 4. bsr.1-0 = reserved for future enhancements. these bits are reserved for future use; mask them out when polling the bsrs. 5. when multiple operations are queued, checking bsr.7 only provides indication of completion for that particular block. gsr.7 provides indication when all queued opera- tions are completed. block status register
8m (512k 16, 1m 8) flash memory lh28f800su 15 * warning: stressing the device bey ond the abso- lute maximum ratings may cause permanent dam- age. these are stress ratings only. operation beyond the operating conditions is not recommended and extended exposure beyond the oper ating conditions may affect device reliability. electrical specifications 1 absolute maximum ratings* temperature under bias ......................... 0c to +80c storage temperature ......................... -65c to +125c v cc = 3.3 v 0.3 v systems 4 symbol parameter min. max. units test conditions note t a operating temperature, commercial 0 70 c ambient temperature 1 v cc v cc with respect to gnd -0.2 7.0 v 2 v pp v pp supply voltage with respect to gnd -0.2 7.0 v 2 v voltage on any pin (except v cc , v pp ) with respect to gnd -0.5 v cc + 0.5 v 2 i current into any non-supply pin 30 ma i out output short circuit current 100.0 ma 3 v cc = 5.0 v 0.5 v systems 4 symbol parameter min. max. units test conditions note t a operating temperature, commercial 0 70 c ambient temperature 1 v cc v cc with respect to gnd -0.2 7.0 v 2 v pp v pp supply voltage with respect to gnd -0.2 7.0 v 2 v voltage on any pin (except v cc , v pp ) with respect to gnd -0.5 7.0 v 2 i current into any non-supply pin 30 ma i out output short circuit current 100.0 ma 3 notes: 1. operating temperature is for commercial product defined by this specification. 2. minimum dc v oltage is -0.5 v on input/output pins. during tr ansitions, this level may undershoot to -2.0 v for periods < 20 ns. maximum dc voltage on input/output pins is v cc + 0.5 v which, during transitions, may overshoot to v cc + 2.0 v for periods < 20 ns. 3. output shorted for no more than one second. no more than one output shorted at a time. 4. ac specifications are valid at both voltage ranges. see dc characteristics tables for voltage range-specific specifications.
lh28f800su 8m (512k 16, 1m 8) flash memory 16 capacitance for 3.3 v systems symbol parameter typ. max. units test conditions note c in capacitance looking into an address/control pin 68 pf t a = 25c, f = 1.0 mhz 1 c out capacitance looking into an output pin 8 12 pf t a = 25c, f = 1.0 mhz 1 c load load capacitance driven by outputs for timing specifications 50 pf for v cc = 3.3 v 0.3 v 1 equivalent testing load circuit 2.5 ns 50 w transmission line delay note: 1. sampled, not 100% tested. capacitance for 5.0 v systems symbol parameter typ. max. units test conditions note c in capacitance looking into an address/control pin 68 pf t a = 25c, f = 1.0 mhz 1 c out capacitance looking into an output pin 8 12 pf t a = 25c, f = 1.0 mhz 1 c load load capacitance driven by outputs for timing specifications 100 pf for v cc = 5.0 v 05 v 1 equivalent testing load circuit v cc 10% 2.5 ns 25 w transmission line delay equivalent testing load circuit v cc 5% 2.5 ns 83 w transmission line delay
8m (512k 16, 1m 8) flash memory lh28f800su 17 timing nomenclature all 3.3 v systems are measured from where signals cross 1.5 v. for 5.0 v systems use the standard jedec cross point definitions. each timing parameter consists of 5 characters. some common examples are defined below: t ce t elqv time (t) from ce ? (e) going low (l) to the outputs (q) becoming valid (v) t oe t glqv time (t) from oe ? (g) going low (l) to the outputs (q) becoming valid (v) t acc t avqv time (t) from address (a) valid (v) to the outputs (q) becoming valid (v) t as t avwh time (t) from address (a) valid (v) to we ? (w) going high (h) t dh t whdx time (t) from we ? (w) going high (h) to when the data (d) can become undefined (x) pin characters pin states a address inputs h high d data inputs l low q data outputs v valid ece ? (chip enable) x driven, but not necessarily valid goe ? (output enable) z high impedance w we (write enable) prp ? (deep power-down pin) rry ? /by ? (ready/busy) v any voltage level y3/5 ? pin 5 v v cc at 4.5 v min. 3 v v cc at 3.0 v min.
lh28f800su 8m (512k 16, 1m 8) flash memory 18 figure 7. transient input/output reference waveform (v cc = 5.0 v) figure 9. transient equivalent testing load circuit (v cc = 3.3 v) figure 8. transient input/output reference waveform (v cc = 3.3 v) 2.5 ns of 50 w transmission line total capacitance = 50 pf from output under test test point 28f800sur-8 figure 10. transient equivalent testing load circuit (v cc = 5.0 v) 2.5 ns of 25 w transmission line total capacitance = 100 pf from output under test test point 28f800sur-9 input test points output 2.4 0.45 2.0 0.8 2.0 0.8 28f800sur-6 note: ac test inputs are driven at v oh (2.4 v ttl ) for a logic '1' and v ol (0.45 v ttl ) for a logic '0'. input timing begins at v ih (2.0 v ttl ) and v il (0.8 v ttl ). output timing ends at v ih and v il . input rise and fall times (10% to 90%) < 10 ns. input test points output 3.0 0.0 1.5 1.5 28f800sur-7 note: ac test inputs are driven at 3.0 v for a logic '1' and 0.0 v for a logic '0'. input timing begins and output timing ends at 1.5 v. input rise and fall times (10% to 90%) < 10 ns. 2.5 ns of 83w transmission line total capacitance = 30 pf from output under test test point 28f800sur-18 figure 11. high speed transient equivalent testing load circuit (v cc = 5.0 v 5%)
8m (512k 16, 1m 8) flash memory lh28f800su 19 dc characteristics v cc = 3.3 v 0.3 v, ta = 0c to +70c 3/5 ? = pin set high for 3.3 v operations symbol parameter typ. min. max. units test conditions note i il input load current 1 a v cc = v cc max., v in = v cc or gnd 1 i lo output leakage current 10 a v cc = v cc max., v in = v cc or gnd 1 i ccs v cc standby current 48a v cc = v cc max., ce ? 0 , ce ? 1 , rp ? = v cc 0.2 v byte, wp, 3/5 ? = v cc 0.2 v or gnd 0.2 v 1,4 14ma v cc = v cc max., ce ? 0 , ce ? 1 , rp ? = v ih byte, wp, 3/5 ? = v ih or v il i ccd v cc deep power-down current 15a rp ? = gnd 0.2 v 1 i ccr 1 v cc read current 30 35 ma v cc = v cc max., cmos: ce ? 0 , ce ? 1 = gnd 0.2 v byte = gnd 0.2 v or v cc 0.2 v inputs = gnd 0.2 v or v cc 0.2 v ttl: ce ? 0 , ce ? 1 = v il, byte = v il or v ih inputs = v il or v ih f = 8 mhz, i out = 0 ma 1, 3, 4 i ccr 2 v cc read current 15 20 ma v cc = v cc max., cmos: ce ? 0 , ce ? 1 = gnd 0.2 v byte = v cc 0.2 v or gnd 0.2 v inputs = gnd 0.2 v or v cc 0.2 v ttl: ce ? 0 , ce ? 1 = v il, byte = v ih or v il inputs = v il or v ih f = 4 mhz, i out = 0 ma 1, 3, 4 i ccw v cc write current 8 12 ma word/byte write in progress 1 i cce v cc block erase current 6 12 ma block erase in progress 1 i cces v cc erase suspend current 36ma ce ? 0 , ce ? 1 = v ih block erase suspended 1, 2 i pps v pp standby current 1 10 a v pp v cc 1 i ppd v pp deep power-down current 0.2 5 a rp ? = gnd 0.2 v 1
lh28f800su 8m (512k 16, 1m 8) flash memory 20 dc characteristics (continued) v cc = 3.3 v 0.3 v, t a = 0c to +70c 3/5 ? = pin set high for 3.3 v operations notes: 1. all currents are in rms unless otherwise noted. typical values at v cc = 3.3 v, v pp = 5.0 v, t = 25c. these currents are valid for all product versions (package and speeds). 2. i cces is specified with the device de-selected. if the device is read while in erase suspend mode, current draw is the sum of i cces and i ccr . 3. automatic power saving (aps) reduces i ccr to less than 1 ma in static operation. 4. cmos inputs are either v cc 0.2 v or gnd 0.2 v. ttl inputs are either v il or v ih . symbol parameter type min. max. units test conditions note i ppr v pp read current 200 a v pp > v cc 1 i ppw v pp write current 40 60 ma v pp = v pph , word/byte write in progress 1 i ppe v pp erase current 20 40 ma v pp = v pph , block erase in progress 1 i ppes v pp erase suspend current 200 a v pp = v pph , block erase suspended 1 v il input low voltage -0.3 0.8 v v ih input high voltage 2.0 v cc + 0.3 v v ol output low voltage 0.4 v v cc = v cc min. and i ol = 4 ma v oh 1 output high voltage 2.4 v i oh = -2.0 ma v cc = v cc min. v oh 2 v cc - 0.2 v i oh = -100 a v cc = v cc min. v ppl v pp during normal operations 0.0 5.5 v v pph v pp during write/erase operations 5.0 4.5 5.5 v v lko v cc erase/write lock voltage 2.0 v
8m (512k 16, 1m 8) flash memory lh28f800su 21 dc characteristics v cc = 5.0 v 0.5 v, t a = 0c to +70c 3/5 ? pin set low for 5 v operations symbol parameter typ. min. max. units test conditions note i il input load current 1 a v cc = v cc max., v in = v cc or gnd 1 i lo output leakage current 10 a v cc = v cc max., v in = v cc or gnd 1 i ccs v cc standby current 510a v cc = v cc max., ce ? 0 , ce ? 1 , rp ? = v cc 0.2 v byte, wp, 3/5 ? = v cc 0.2 v or gnd 0.2 v 1,4 24ma v cc = v cc max., ce ? 0 , ce ? 1 , rp ? = v ih byte, wp, 3/5 ? = v ih or v il i ccd v cc deep power-down current 15a rp ? = gnd 0.2 v 1 i ccr 1 v cc read current 50 60 ma v cc = v cc max., cmos: ce ? 0 , ce ? 1 = gnd 0.2 v byte = gnd 0.2 v or v cc 0.2 v inputs = gnd 0.2 v or v cc 0.2 v ttl: ce ? 0 , ce ? 1 = v il, byte = v il or v ih inputs = v il or v ih f = 10 mhz, i out = 0 ma 1, 3, 4 i ccr 2 v cc read current 30 35 ma v cc = v cc max., cmos: ce ? 0 , ce ? 1 = gnd 0.2 v byte = v cc 0.2 v or gnd 0.2 v inputs = gnd 0.2 v or v cc 0.2 v ttl: ce ? 0 , ce ? 1 = v il, byte = v ih or v il inputs = v il or v ih f = 5 mhz, i out = 0 ma 1, 3, 4 i ccw v cc write current 25 35 ma word/byte write in progress 1 i cce v cc block erase current 18 25 ma block erase in progress 1 i cces v cc erase suspend current 510ma ce ? 0 , ce ? 1 = v ih block erase suspended 1, 2 i pps v pp standby current 10 a v pp v cc 1 i ppd v pp deep power-down current 0.2 5 a rp ? = gnd 0.2 v 1
lh28f800su 8m (512k 16, 1m 8) flash memory 22 dc characteristics (continued) v cc = 5.0 v 0.5 v, t a = 0c to +70c 3/5 ? pin set low for 5 v operations notes: 1. all currents are in rms unless otherwise noted. typical values at v cc = 5.0 v, v pp = 5.0 v, t = 25c. these currents are valid for all product versions (package and speeds). 2. i cces is specified with the device de-selected. if the device is read while in erase suspend mode, current draw is the sum of i cces and i ccr . 3. automatic power saving (aps) reduces i ccr to less than 2 ma in static operation. 4. cmos inputs are either v cc 0.2 v or gnd 0.2 v. ttl inputs are either v il or v ih . symbol parameter type min. max. units test conditions note i ppr v pp read current 65 200 a v pp > v cc 1 i ppw v pp write current 40 60 ma v pp = v pph , word/byte write in progress 1 i ppe v pp erase current 20 40 ma v pp = v pph , block erase in progress 1 i ppes v pp erase suspend current 65 200 a v pp = v pph , block erase suspended 1 v il input low voltage -0.5 0.8 v v ih input high voltage 2.0 v cc + 0.5 v v ol output low voltage 0.45 v v cc = v cc min. and i ol = 5.8 ma v oh 1 output high voltage 0.85 v cc v i oh = -2.5 ma v cc = v cc min. v oh 2 v cc - 0.4 v i oh = -100 a v cc = v cc min. v ppl v pp during normal operations 0.0 5.5 v v pph v pp during write/erase operations 5.0 4.5 5.5 v v lko v cc erase/write lock voltage 2.0 v
8m (512k 16, 1m 8) flash memory lh28f800su 23 ac characteristics - read only operations 1 t a = 0c to +70c symbol parameter v cc = 3.3 v 0.3v v cc = 2.7 - 3.6 v units note min. max. min. max. t avav read cycle time 120 160 ns t avel address setup to ce ? going low 10 10 ns 3, 4 t avgl address setup to oe ? going low 0 0 ns 3, 4 t avqv address to output delay 120 160 ns t elqv ce ? to output delay 120 160 ns 2 t phqv rp ? high to output delay 620 650 ns t glqv oe ? to output delay 45 45 ns 2 t elqx ce ? to output in low z 0 0 ns 3 t ehqz ce ? to output in high z 50 50 ns 3 t glqx oe ? to output in low z 0 0 ns 3 t ghqz oe ? to output in high z 30 30 ns 3 t oh output hold from address, ce ? or oe ? change, whichever occurs first 00ns3 t flqv t fhqv byte to output delay 120 160 ns 3 t flqz byte low to output in high z 30 30 ns 3 t elfl t elfh ce ? low to byte high or low 5 5 ns 3
lh28f800su 8m (512k 16, 1m 8) flash memory 24 ac characteristics - read only operations 1 (continued) t a = 0c to +70c symbol parameter v cc = 5.0 v 0.25v v cc = 5.0 v 0.5v units note min. max. min. max. t avav read cycle time 70 80 ns t avel address setup to ce ? going low 10 10 ns 3, 4 t avgl address setup to oe ? going low 0 0 ns 3, 4 t avqv address to output delay 70 80 ns t elqv ce ? to output delay 70 80 ns 2 t phqv rp ? high to output delay 400 480 ns t glqv oe ? to output delay 30 35 ns 2 t elqx ce ? to output in low z 0 0 ns 3 t ehqz ce ? to output in high z 25 30 ns 3 t glqx oe ? to output in low z 0 0 ns 3 t ghqz oe ? to output in high z 25 30 ns 3 t oh output hold from address, ce ? or oe ? change, whichever occurs first 0 0 ns 3 t flqv t fhqv byte to output delay 70 80 ns 3 t flqz byte low to output in high z 25 30 ns 3 t elfl t elfh ce ? low to byte high or low 5 5 ns 3 notes: 1. see ac input/output reference waveforms for timing measurements. 2. oe ? may be delayed up to t elqv - t glqv after the falling edge of ce ? without impact on t elqv . 3. sampled, not 100% tested. 4. this timing parameter is used to latch the correct bsr data onto the outputs.
8m (512k 16, 1m 8) flash memory lh28f800su 25 figure 12. read timing waveforms 28f800sur-10 t avav note: ce x is defined as the latter of ce 0 or ce 1 going low or the first of ce 0 or ce 1 going high. addresses stable v cc power-up standby device and address selection outputs enabled data valid standby v cc power-down t avel addresses (a) v ih v il ce x (e) (note) v ih v il t avgl t glqv t elqv t glqx t elqx t avqv t phqv t ehqz t ghqz t oh oe (g) v ih v il we (w) v ih v il data (d/q) v oh v ol v cc 5.0 v gnd rp (p) v ih v il high-z high-z valid output . . . . . . . . . . . . . . . . . . . . .
lh28f800su 8m (512k 16, 1m 8) flash memory 26 figure 13. by ? te ? timing waveforms 28f800sur-11 t avav note: ce x is defined as the latter of ce 0 or ce 1 going low or the first of ce 0 or ce 1 going high. addresses stable t avfl = t elfl addresses (a) v ih v il ce x (e) (note) v ih v il t ehqz oe (g) v ih v il data (dq 0 - dq 7 ) v oh v ol high-z high-z byte (f) v ih v il v oh v ol high-z high-z data output data output data output t avel t avgl t elfl t flqv = t avqv t glqv t ghqz t elqv t elqx t glqx t oh t avqv t flqz data (dq 8 - dq 15 ) . . . . . . . . . . . . . . . . . . . . .
8m (512k 16, 1m 8) flash memory lh28f800su 27 figure 14. v cc power-up and rp ? reset waveforms valid address (a) data (q) rp (p) 3/5 (y) v cc (3 v, 5 v) address (a) data (q) rp (p) valid valid valid valid valid t plph t avqv t phqv t plph t ylph t plyl t yhph t 5vph t pl5v t 3vph t avqv t phqv t phqv t avqv 4.5 v 5.0 v 3.0 v 0 v 3.3 v 28f800sur-12
lh28f800su 8m (512k 16, 1m 8) flash memory 28 notes: ce ? 0 , ce ? 1 and oe ? are switched low after power-up. 1. minimum of 2 s is required to meet the specified t phqv times. 2. the power supply may start to switch concurrently with rp ? going low. rp ? is required to stay low, until v cc stays at recommended operating voltage. 3. the address access time and rp ? high to data valid time are shown for 5 v v cc operation. refer to the ac characteristics read only operations 3.3 v v cc operation and all other speed options. symbol parameter min. max. unit note t plyl t plyh rp ? low to 3/5 ? low (high) 0 s t ylph t yhph 3/5 ? low (high) to rp ? high 2 s 1 t pl5v t pl3v rp ? low to v cc at 4.5 v min. (to v cc at 3.0 v min or 3.6 v max.) 0s2 t plph rp ? 'low' 100 ns t 5vph v cc at 4.5 v to rp ? high 100 ns 3 t 3vph v cc at 3.0 v to rp ? high 100 ns 3 t avqv address valid to data valid for v cc = 5 v 10% 100 ns 4 t phqv rp ? high to data valid for v cc = 5 v 10% 480 ns 4
8m (512k 16, 1m 8) flash memory lh28f800su 29 ac characteristics for we ? - controlled command write operations 1 t a = 0c to +70c symbol parameter typ. v cc = 3.3 0.3 v note min. max. units t avav write cycle time 120 ns t vpwh v pp setup to we going high 100 ns 3 t phel rp ? setup to ce ? going low 480 ns t elwl ce ? setup to we going low 10 ns t avwh address setup to we going high 75 ns 2, 6 t dvwh data setup to we going high 75 ns 2, 6 t wlwh we pulse width 75 ns t whdx data hold from we high 10 ns 2 t whax address hold from we high 10 ns 2 t wheh ce ? hold from we high 10 ns t whwl we pulse width high 45 ns t ghwl read recovery before write 0 ns t whrl we high to ry ? /by ? going low 100 ns t rhpl rp ? hold from valid status register (csr, gsr, bsr) data and ry ? /by ? high 0ns3 t phwl rp ? high recovery to we going low 1s t whgl write recovery before read 95 ns t qvvl v pp hold from valid status register (csr, gsr, bsr) data and ry ? /by ? high 0s t whqv 1 duration of word/byte write operation 12 5 s 4, 5 t whqv 2 duration of block erase operation 0.3 s 4
lh28f800su 8m (512k 16, 1m 8) flash memory 30 ac characteristics for we ? - controlled command write operations 1 (continued) t a = 0c to +70c symbol parameter v cc = 5.0 0.25 v v cc = 5.0 0.5 v units note typ. min. max. typ. min. max. t avav write cycle time 70 80 ns t vpwh v pp setup to we going high 100 100 ns 3 t phel rp ? setup to ce ? going low 480 480 ns t elwl ce ? setup to we going low 0 0 ns t avwh address setup to we going high 50 50 ns 2, 6 t dvwh data setup to we going high 50 50 ns 2, 6 t wlwh we pulse width 40 50 ns t whdx data hold from we high 0 0 ns 2 t whax address hold from we high 10 10 ns 2 t wheh ce ? hold from we high 10 10 ns t whwl we pulse width high 30 30 ns t ghwl read recovery before write 0 0 ns t whrl we high to ry ? /by ? going low 100 100 ns t rhpl rp ? hold from valid status register (csr, gsr, bsr) data and ry ? /by ? high 00ns3 t phwl rp ? high recovery to we going low 1 1 s t whgl write recovery before read 60 65 ns t qvvl v pp hold from valid status register (csr, gsr, bsr) data and ry ? /by ? high 00s t whqv 1 duration of word/byte write operation 8 4.5 8 4.5 s 4, 5 t whqv 2 duration of block erase operation 0.3 0.3 s 4 notes: ce ? is defined as the latter of ce ? 0 or ce ? 1 going low or the first of ce ? 0 or ce ? 1 going high. 1. read timing during write and erase are the same as for normal read. 2. refer to command definition tables for valid address and data values. 3. sampled, but not 100% tested. 4. write/erase durations are measured to valid status register (csr) data. 5. word/byte write operations are typically performed with 1 programming pulse. 6. address and data are latched on the rising edge of ce ? for all command write operations.
8m (512k 16, 1m 8) flash memory lh28f800su 31 figure 15. ac waveforms for command write operations addresses (a) (note 1) v ih v il a in a = ra v ih v il a in a = ra d in d in d in d in d out ce x (e) (note 4) v ih v il oe (g) v ih v il we (w) v ih v il data (d/q) v ih v il ry/by (r) v oh v ol rp (p) v ih v il v pp (v) v pph v ppl t avav t avav t whgl t whwl t wlwh t dvwh t phwl t rhpl t qvvl addresses (a) (note 2) t avwh t whax t avwh t whax t elwl t wheh t whqv1, 2 t ghwl t whdx t whrl (note 5) t vpwh 28f800sur-13 (note 3) high-z write data-write or erase setup command deep power-down write valid address and data (data-write) or erase confirm command automated data-write or erase delay write read extended register command read extended status register data notes: 1. this address string depicts data-write/erase cycles with corresponding verification via esrd. 2. this address string depicts data-write/erase cycles with corresponding verification via csrd. 3. this cycle is invalid when using csrd for verification during data-write/erase operations. 4. ce x is defined as the latter of ce 0 or ce 1 going low or the first of ce 0 or ce 1 going high. 5. rp low transition is only to show t rhpl ; not valid for above read and write cycles. read compatible status register data
lh28f800su 8m (512k 16, 1m 8) flash memory 32 ac characteristics for ce ? - controlled command write operations 1 t a = 0c to +70c symbol parameter v cc = 3.3 v 0.3 v units note typ. min. max. t avav write cycle time 120 ns t phwl rp ? setup to we going low 480 ns 3 t vpeh v pp setup to ce ? going high 100 ns 3 t wlel we setup to ce ? going low 0 ns t aveh address setup to ce ? going high 75 ns 2, 6 t dveh data setup to ce ? going high 75 ns 2, 6 t eleh ce ? pulse width 75 ns t ehdx data hold from ce ? high 10 ns 2 t ehax address hold from ce ? high 10 ns 2 t ehwh we hold from ce ? high 10 ns t ehel ce ? pulse width high 45 ns t ghel read recovery before write 0 ns t ehrl ce ? high to ry ? /by ? going low 100 ns t rhpl rp ? hold from valid status register (csr, gsr, bsr) data and ry ? /by ? high 0ns3 t phel rp ? high recovery to ce ? going low 1 s t ehgl write recovery before read 95 ns t qvvl v pp hold from valid status register (csr, gsr, bsr) data and ry ? /by ? high 0s t ehqv 1 duration of word/byte write operation 12 5 s 4, 5 t ehqv 2 duration of block erase operation 0.3 s 4
8m (512k 16, 1m 8) flash memory lh28f800su 33 notes: ce ? is defined as the latter of ce ? 0 or ce ? 1 going low or the first of ce ? 0 or ce ? 1 going high. 1. read timing during write and erase are the same as for normal read. 2. refer to command definition tables for valid address and data values. 3. sampled, but not 100% tested. 4. write/erase durations are measured to valid status register (csr) data. 5. word/byte write operations are typically performed with 1 programming pulse. 6. address and data are latched on the rising edge of ce ? for all command write operations. ac characteristics for ce ? - controlled command write operations 1 (continued) t a = 0c to +70c symbol parameter v cc = 5.0 v 0.25 v v cc = 5.0 v 0.5 v units note typ. min. max. typ. min. max. t avav write cycle time 70 80 ns t phwl rp ? setup to we going low 480 480 ns 3 t vpeh v pp setup to ce ? going high 100 100 ns 3 t wlel we setup to ce ? going low 0 0 ns t aveh address setup to ce ? going high 50 50 ns 2, 6 t dveh data setup to ce ? going high 50 50 ns 2, 6 t eleh ce ? pulse width 40 50 ns t ehdx data hold from ce ? high 0 0 ns 2 t ehax address hold from ce ? high 10 10 ns 2 t ehwh we hold from ce ? high 10 10 ns t ehel ce ? pulse width high 30 30 ns t ghel read recovery before write 0 ns t ehrl ce ? high to ry ? /by ? going low 100 100 ns t rhpl rp ? hold from valid status register (csr, gsr, bsr) data and ry ? /by ? high 00ns3 t phel rp ? high recovery to ce ? going low 1 1 s t ehgl write recovery before read 60 65 ns t qvvl v pp hold from valid status register (csr, gsr, bsr) data and ry ? /by ? high 00s t ehqv 1 duration of word/byte write operation 8 4.5 4.5 s 4, 5 t ehqv 2 duration of block erase operation 0.3 0.3 s 4
lh28f800su 8m (512k 16, 1m 8) flash memory 34 figure 16. alternate ac waveforms for command write operations addresses (a) (note 1) v ih v il a in a = ra v ih v il a in d in d in d in d in d out ce x (e) (note 4) v ih v il oe (g) v ih v il we (w) v ih v il data (d/q) v ih v il ry/by (r) v oh v ol rp (p) v ih v il v pp (v) v pph v ppl t avav t avav t ehgl t ehel t eleh t dveh t phel t rhpl t qvvl addresses (a) (note 2) t aveh t ehax t aveh t ehax t wlel t ehwh t ehqv1, 2 t ghel t ehdx t ehrl (note 5) t vpeh 28f800sur-14 (note 3) high-z write data-write or erase setup command deep power-down write valid address and data (data-write) or erase confirm command automated data-write or erase delay write read extended register command notes: 1. this address string depicts data-write/erase cycles with corresponding verification via esrd. 2. this address string depicts data-write/erase cycles with corresponding verification via csrd. 3. this cycle is invalid when using csrd for verification during data-write/erase operations. 4. ce x is defined as the latter of ce 0 or ce 1 going low or the first of ce 0 or ce 1 going high. 5. rp low transition is only to show t rhpl ; not valid for above read and write cycles. read extended status register data read compatible status register data
8m (512k 16, 1m 8) flash memory lh28f800su 35 ac characteristics for page buffer write operations 1 t a = 0c to +70c symbol parameter v cc = 3.3 v 0.3 v units note typ. min. max. t avav write cycle time 120 ns t elwl ce ? setup to we going low 10 ns t avwl address setup to we going low 0 ns 3 t dvwh data setup to we going high 75 ns 2 t wlwh we pulse width 75 ns t whdx data hold from we high 10 ns 2 t whax address hold from we high 10 ns 2 t wheh ce ? hold from we high 10 ns t whwl we pulse width high 45 ns t ghwl read recovery before write 0 ns t whgl write recovery before read 95 ns symbol parameter v cc = 5.0 v 0.25 v v cc = 5.0 v 0.5 v units note typ. min. max. typ. min. max. t avav write cycle time 70 80 ns t elwl ce ? setup to we going low 0 0 ns t avwl address setup to we going low 0 0 ns 3 t dvwh data setup to we going high 50 50 ns 2 t wlwh we pulse width 40 50 ns t whdx data hold from we high 0 0 ns 2 t whax address hold from we high 10 10 ns 2 t wheh ce ? hold from we high 10 10 ns t whwl we pulse width high 30 30 ns t ghwl read recovery before write 0 0 ns t whgl write recovery before read 60 65 ns notes: ce ? is defined as the latter of ce ? 0 or ce ? 1 going low or the first of ce ? 0 or ce ? 1 going high. 1. these are we ? controlled write timings, equivalent ce ? controlled write timings apply. 2. sampled, but not 100% tested. 3. address must be valid during the entire we ? low pulse.
lh28f800su 8m (512k 16, 1m 8) flash memory 36 figuer 17. page buffer write timing waveforms erase and word/byte write performance v cc = 3.3 v 0.3 v, t a = 0c to +70c symbol parameter typ. (1) min. max. units test conditions note t whrh 1 word/byte write time 12 s 2 t whrh 2 block write time 0.8 2.1 s byte write mode 2 t whrh 3 block write time 0.4 1.0 s word write mode 2 block erase time 0.9 10 s 2 full chip erase time 14.4 s 2 notes: 1. 25c, v pp = 5.0 v. 2. excludes system-level overhead. v cc = 5.0 v 0.5 v, t a = 0c to +70c symbol parameter typ. (1) min. max. units test conditions note t whrh 1 word/byte write time 8 s 2 t whrh 2 block write time 0.54 2.1 s byte write mode 2 t whrh 3 block write time 0.27 1.0 s word write mode 2 block erase time 0.7 10 s 2 full chip erase time 11.2 s 2 valid addresses (a) high-z d in t dvwh data (d/q) ce x (e) we (w) t whdx t avwl t wlwh t whwl t wheh t elwl t whax 28f800sur-15
8m (512k 16, 1m 8) flash memory lh28f800su 37 ordering information 56 0.50 [0.020] typ. 29 28 1 package base plane 0.28 [0.011] 0.12 [0.005] 20.30 [0.799] 19.70 [0.776] 18.60 [0.732] 18.20 [0.717] 19.30 [0.760] 18.70 [0.736] 0.49 [0.019] 0.39 [0.015] 0.22 [0.009] 0.02 [0.001] 1.10 [0.043] 0.90 [0.035] 1.19 [0.047] max. 0.13 [0.005] 0.18 [0.007] 0.08 [0.003] 14.20 [0.559] 13.80 [0.543] 56tsop 56tsop (tsop056-p-1420) dimensions in mm [inches] maximum limit minimum limit 56-pin, 1.2 mm x 14 mm x 20 mm tsop (type i) (tsop056-p-1420) lh28f800su device type t package 28f800sur-16 example: LH28F800SUT-70 (8m (512k x 16, 1m x 8) flash memory, 70 ns, 56-pin tsop) 8m (512k x 16, 1m x 8) flash memory -## speed 70 access time (ns)
sharp reserves the right to make changes in specifications at any time and without notice. sharp does not assume any responsibility for the use of any circuitry described; no circuit patent licenses are implied. north america europe asia sharp electronics corporation microelectronics group 5700 nw pacific rim blvd., m/s 20 camas, wa 98607, u.s.a. phone: (360) 834-2500 telex: 49608472 (sharpcam) facsimile: (360) 834-8903 http://www.sharpmeg.com sharp electronics (europe) gmbh microelectronics division sonninstra? 3 20097 hamburg, germany phone: (49) 40 2376-2286 telex: 2161867 (heeg d) facsimile: (49) 40 2376-2232 life support policy sharp components should not be used in medical devices with life support functions or in safety equipment (or similiar applications where component failure would result in loss of life or physical harm) without the written approval of an officer of the sharp corporation. sharp corporation integrated circuits group 2613-1 ichinomoto-cho tenri-city, nara, 632, japan phone: (07436) 5-1321 telex: labometa-b j63428 facsimile: (07436) 5-1532 warranty sharp warrants to customer that the products will be free from defects in material and workmanship under normal use and service for a period of one year from the date of invoice. customer's exclusive remedy for breach of this warranty is that sharp will either (i) repair or replace, at its option, any product which fails during the warranty period because of such defect (if customer promptly reported the failure to sharp in writing) or, (ii) if sharp is unable to repair or replace, sharp will refund the purchase price of the product upon its return to sharp . this warranty does not apply to any product which has been subjected to misuse, abnormal service or handling, or which has been altered or modified in design or construction, or which has been serviced or repaired by anyone other than sharp . the warranties set forth herein are in lieu of, and exclusive of, all other warranties, express or implied. all express and implied warranties of merchantability, fitness for use and fitness for a particular purpose are specifically excluded. ? ?1997 by sharp corporation reference code smt96107 issued may 1996 lh28f800su 8m (512k 16, 1m 8) flash memory

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